Modeling and emulation impact
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§ Multiple software and FPGA-based methods have been essential to IBM’s full-stack AIU and AI
system development
§ Our SoC design process leverages multiple levels of simulation for architecture development, logic and
chip design, and design verification
§ Our software stack development, accelerator software integration development, and compiler /
hardware co-optimization leveraged FPGA-based emulation systems
§ Full-chip emulation via ZeBu for full-chip performance & accuracy analyses of AI models on multi-
core models, compiler optimizations, architectural modifications and power estimation
§ Detailed SoC nest emulation via HAPS for device driver development, low-level software stack
development, and evaluation of multi-chip configurations
§ These methods enabled us to develop a full system, end-to-end hardware and software stack for
Foundation Model inference in parallel to SoC and PCIe card development
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